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1 data sheet 8 mbit / 16 mbit (x8) multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ? 2000 silicon storage technology, inc.the sst logo and superflash are registered trademarks of silicon storage technology, inc . mpf is a trademark of silicon storage technology, inc. 396-2 11/00 s71146 these specifications are subject to change without notice. features: ? organized as 1m x8 / 2m x8 single voltage read and write operations - 3.0-3.6v for sst39lf080/016 - 2.7-3.6v for sst39vf080/016 superior reliability - endurance: 100,000 cycles (typical) - greater than 100 years data retention low power consumption: - active current: 15 ma (typical) - standby current: 4 a (typical) - auto low power mode: 4 a (typical) sector-erase capability - uniform 4 kbyte sectors block-erase capability - uniform 64 kbyte blocks fast read access time: - 55 ns for sst39lf080/016 - 70 and 90 ns for sst39vf080/016 latched address and data fast erase and byte-program: - sector-erase time: 18 ms (typical) - block-erase time: 18 ms (typical) - chip-erase time: 70 ms (typical) - byte-program time: 14 s (typical) - chip rewrite time: 15 seconds (typical) for sst39lf/vf080 30 seconds (typical) for sst39lf/vf016 automatic write timing - internal v pp generation end-of-write detection - toggle bit - data# polling cmos i/o compatibility jedec standard - flash eeprom pinouts and command sets packages available - 40-pin tsop (10mm x 20mm) - 48-ball tfbga (6mm x 8mm) product description the sst39lf/vf080 and sst39lf/vf016 devices are 1m x8 / 2m x8 cmos multi-purpose flash (mpf) manufactured with sst?s proprietary, high performance cmos superflash technology. the split-gate cell de- sign and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39lf080/016 write (program or erase) with a 3.0-3.6v power supply. the sst39vf080/016 write (program or erase) with a 2.7- 3.6v power supply. they conform to jedec standard pinouts for x8 memories. featuring high performance byte-program, the sst39lf/vf080 and sst39lf/vf016 devices provide a typical byte-program time of 14 sec. the devices use toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and software data protec- tion schemes. designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst39lf/vf080 and sst39lf/vf016 devices are suited for applications that require convenient and eco- nomical updating of program, configuration, or data memory. for all system applications, they significantly improve performance and reliability, while lowering power consumption. they inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technologies. they also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of erase/ program cycles that have occurred. therefore the sys- tem software or hardware does not have to be modified or de-rated as is necessary with alternative flash tech- nologies, whose erase and program times increase with accumulated erase/program cycles. to meet high density, surface mount requirements, the sst39lf/vf080 and sst39lf/vf016 are offered in 40-pin tsop and 48-ball tfbga packaging. see figures 1 and 2 for pinouts. device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write se- quences. a command is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first.
2 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 the sst39lf/vf080 and sst39lf/vf016 also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 15 ma to typically 4 a. the auto low power mode reduces the typical i dd active read current to the range of 1 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto low power mode after power-up with ce# held steadily low until the first address transition or ce# is driven high. read the read operation of the sst39lf/vf080 and sst39lf/vf016 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 3). byte-program operation the sst39lf/vf080 and sst39lf/vf016 are pro- grammed on a byte-by-byte basis. the program operation consists of three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte- program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed within 20 s. see figures 4 and 5 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. sector/block-erase operation the sector- (or block-) erase operation allows the sys- tem to erase the device on a sector-by-sector (or block- by-block) basis. the sst39lf/vf080 and sst39lf/ vf016 offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 4 kbyte. the block-erase mode is based on uniform block size of 64 kbyte. the sector-erase operation is initiated by executing a six-byte-command sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte-command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figures 9 and 10 for timing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the sst39lf/vf080 and sst39lf/vf016 provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 8 for timing diagram, and figure 19 for the flowchart. any commands issued during the chip-erase operation are ignored. write operation status detection the sst39lf/vf080 and sst39lf/vf016 provide two software means to detect the completion of a write (pro- gram or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end- of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase opera- tion. the actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
3 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 data# polling (dq 7 ) when the sst39lf/vf080 and sst39lf/vf016 are in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. the device is then ready for the next operation. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1?s and 0?s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for toggle bit timing diagram and figure 17 for a flowchart. data protection the sst39lf/vf080 and sst39lf/vf016 provide both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf/vf080 and sst39lf/vf016 provide the jedec approved software data protection scheme for all data alteration operations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., dur- ing the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst39lf/vf080 and sst39lf/vf016 devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode within t rc . common flash memory interface (cfi) the sst39lf/vf080 and sst39lf/vf016 also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write three-byte sequence, same as product id entry command with 98h (cfi query command) to address 5555h in the last byte sequence. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the device as the sst39lf080, sst39vf080, sst39lf016 and sst39vf016 and manufacturer as sst. this mode may be accessed by hardware or software operations. the hardware operation is typically used by a programmer to identify the correct algorithm for the sst39lf/vf080 and sst39lf/ vf016. users may wish to use the software product identifi- cation operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 3 for hardware operation or table 4 for software operation, figure 11 for the software id entry and read timing diagram and figure 18 for the software id entry command sequence flowchart. product identification mode exit/cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accomplished by issuing the software id exit command sequence, which returns the device to the read operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 13 for timing waveform and figure 18 for a flowchart. t able 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst39lf/vf080 0001h d8h sst39lf/vf016 0001h d9h 396 pgm t1.2
4 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 1: p in a ssignments for 40- pin tsop f unctional b lock d iagram sst39lf/vf080 sst39lf/vf016 a16 a15 a14 a13 a12 a11 a9 a8 we# nc nc nc a18 a7 a6 a5 a4 a3 a2 a1 a16 a15 a14 a13 a12 a11 a9 a8 we# nc nc nc a18 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a17 v ss nc a19 a10 dq7 dq6 dq5 dq4 v dd v dd nc dq3 dq2 dq1 dq0 oe# v ss ce# a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 396 ill f01.2 standard pinout top view die up sst39lf/vf160 sst39lf/vf080 a17 v ss a20 a19 a10 dq7 dq6 dq5 dq4 v dd v dd nc dq3 dq2 dq1 dq0 oe# v ss ce# a0 f igure 2: p in a ssignments for 48- ball tfbga y-decoder i/o buffers and data latches 396 ill b1.2 address buffer & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic a14 a9 we# nc a7 a3 a13 a8 nc nc a18 a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 a17 a19 dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# a20 dq6 v dd v dd nc oe# v ss dq7 dq4 nc dq1 v ss 396 ill f20.0 sst39lf/vf080 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h a14 a9 we# nc a7 a3 a13 a8 nc nc a18 a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 a17 a19 dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# a20 dq6 v dd v dd nc oe# v ss dq7 dq4 a21 dq1 v ss 396 ill f21.0 sst39lf/vf016 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h
5 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 t able 3: o peration m odes s election mode ce# oe# we# a9 dq address read v il v il v ih a in d out a in program v il v ih v il a in d in a in erase v il v ih v il x x sector or block address, xxh for chip-erase standby v ih x x x high z x write inhibit x v il x x high z/ d out x xxv ih x high z/ d out x product identification hardware mode v il v il v ih v h manufacturer's id (bfh) a ms (2) - a 1 = v il , a 0 = v il device id (1) a 20 (2) - a 1 = v il , a 0 = v ih software mode v il v il v ih a in see table 4 notes: (1) device id d8h for sst39lf/vf080 and d9h for sst39lf/vf016 (2) a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 396 pgm t3.2 t able 2: p in d escription symbol pin name functions a ms -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. during block-erase a ms -a 16 address lines will select the block. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 3.0-3.6v for sst39lf080/016 2.7-3.6v for sst39vf080/016 vss ground nc no connection unconnected pins. note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 396 pgm t2.2
6 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 t able 5: cfi q uery i dentification s tring 1 for sst39lf/vf080 and sst39lf/vf016 address data data 10h 51h 11h 52h query unique ascii string ? qry ? 12h 59h 13h 01h primary oem command set 14h 07h 15h 00h address for primary extended table 16h 00h 17h 00h alternate oem command set (00h = none exists) 18h 00h 19h 00h address for alternate oem extended table (00h = none exits) 1ah 00h note 1: refer to cfi publication 100 for more details. 396 pgm t5.3 t able 4: s oftware c ommand s equence command 1st bus 2nd bus 3rd bus 4th bus 5th bus 6th bus sequence write cycle write cycle write cycle write cycle write cycle write cycle addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data byte-program 5555h aah 2aaah 55h 5555h a0h wa (3) data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x (2) 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x (2) 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5555h aah 2aaah 55h 5555h 90h cfi query entry 5555h aah 2aaah 55h 5555h 98h software id exit/ xxh f0h cfi exit software id exit/ 5555h aah 2aaah 55h 5555h f0h cfi exit notes: (1) address format a 14 -a 0 (hex), addresses a 15, a 16, a 17, a 18 and a 19 are ? don ? t care ? for command sequence for sst39lf/vf080. addresses a 15, a 16, a 17, a 18, a 19 and a 20 are ? don ? t care ? for command sequence for sst39lf/vf016. (2) sa x for sector-erase; uses a ms -a 12 address lines ba x , for block-erase; uses a ms -a 16 address lines a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. (3) wa = program byte address (4) both software id exit operations are equivalent notes for software id entry command sequence 1. with a ms -a 1 = 0; sst manufacturer's id = bfh, is read with a 0 = 0, sst39lf/vf080 device id = d8h, is read with a 0 = 1. sst39lf/vf016 device id = d9h, is read with a 0 = 1. a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 2. the device does not remain in software product id mode if powered down. 396 pgm t4.1
7 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 t able 7 b : d evice g eometry i nformation for sst39lf/vf016 address data data 27h 15h device size = 2 n byte (15h = 21; 2 21 = 2m bytes) 28h 00h flash device interface description; 0000h = x8-only asynchronous interface 29h 00h 2ah 00h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 00h 2ch 02h number of erase sector/block sizes supported by device 2dh ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 01h y = 511 + 1 = 512 sectors (01ffh = 511) 2fh 10h 30h 00h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 1fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 00h y = 31 + 1 = 32 blocks (001fh = 31) 33h 00h 34h 01h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) 396 pgm t7b.1 t able 7 a : d evice g eometry i nformation for sst39lf/vf080 address data data 27h 14h device size = 2 n bytes (14h = 20; 2 20 = 1m bytes) 28h 00h flash device interface description; 0000h = x8-only asynchronous interface 29h 00h 2ah 00h maximum number of byte in multi-byte write = 2 n (00h = not supported) 2bh 00h 2ch 02h number of erase sector/block sizes supported by device 2dh ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 00h y = 255 + 1 = 256 sectors (00ffh = 255) 2fh 10h 30h 00h z = 16 x 256 bytes = 4 kbytes/sector (0010h = 16) 31h 0fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 00h y = 15 + 1 = 16 blocks (000fh = 15) 33h 00h 34h 01h z = 256 x 256 bytes = 64 kbytes/block (0100h = 256) 396 pgm t7a.0 396 pgm t6.1 t able 6: s ystem i nterface i nformation for sst39lf/vf080 and sst39lf/vf016 address data data 1bh 27h 1) v dd min. (program/erase) 30h (1) dq7-dq4: volts, dq3-dq0: 100 millivolts 1ch 36h v dd max. (program/erase) dq7-dq4: volts, dq3-dq0: 100 millivolts 1dh 00h v pp min. (00h = no v pp pin) 1eh 00h v pp max. (00h = no v pp pin) 1fh 04h typical time out for byte-program 2 n s (2 4 = 16 s) 20h 00h typical time out for min. size buffer program 2 n s (00h = not supported) 21h 04h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 06h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 01h maximum time out for byte-program 2 n times typical (2 1 x 2 4 = 32 s) 24h 00h maximum time out for buffer program 2 n times typical 25h 01h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 01h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) note (1) 30h for sst39lf080/016 and 27h for sst39vf080/016
8 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 absolute maximum stress ratings (applied conditions greater than those listed under ? absolute maximum stress ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias ......................................................................................................... ........ -55 c to +125 c storage temperature ............................................................................................................ .......... -65 c to +150 c d. c. voltage on any pin to ground potential ............................................................................ -0.5v t o v dd + 0.5v transient voltage (<20 ns) on any pin to ground potential ........................................................ -1.0v to v dd + 1.0v voltage on a 9 pin to ground potential ................................................................................................ -0.5v to 13.2v package power dissipation capability (ta = 25 c) ........................................................................................... 1.0w surface mount lead soldering temperature (3 seconds) ........................................................................... .... 240 c output short circuit current (1) ............................................................................................................................... .................................. 50 ma note: (1) outputs shorted for no more than one second. no more than one output shorted at a time. ac c onditions of t est input rise/fall time ......... 5 ns output load ..................... c l = 30 pf for sst39lf080/016 ........................................ c l = 100 pf for sst39vf080/016 see figures 14 and 15 o perating r ange for sst39vf080/016 range ambient temp v dd commercial 0 c to +70 c 2.7 - 3.6v industrial -40 c to +85 c 2.7 - 3.6v o perating r ange for sst39lf080/016 range ambient temp v dd commercial 0 c to +70 c 3.0 - 3.6v
9 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 396 pgm t10.1 t able 9: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read (1) power-up to read operation 100 s t pu-write (1) power-up to program/erase 100 s operation note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this para meter. 396 pgm t11.0 t able 10: c apacitance (ta = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o (1) i/o pin capacitance v i/o = 0v 12 pf c in (1) input capacitance v in = 0v 6 pf note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this para meter. t able 8: dc o perating c haracteristics v dd = 3.0-3.6v for sst39lf080/016 and 2.7-3.6v for sst39vf080/016 limits symbol parameter min max units test conditions i dd power supply current address input = v il /v ih , at f=1/t rc min., v dd =v dd max. read 20 ma ce#=oe#=v il, we#=v ih , all i/os open program and erase 25 ma ce#=we#=v il, oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd = v dd max. i alp auto low power current 20 a ce#=v ilc , v dd = v dd max. all inputs = v ihc or v ilc we# = v ihc i li input leakage current 1 a v in =gnd to v dd , v dd = v dd max. i lo output leakage current 1 a v out =gnd to v dd , v dd = v dd max. v il input low voltage 0.8 v v dd = v dd min. v ilc input low voltage (cmos) 0.3 v v dd = v dd max. v ih input high voltage 0.7 v dd vv dd = v dd max. v ihc input high voltage (cmos) v dd -0.3 v v dd = v dd max. v ol output low voltage 0.2 v i ol = 100 a, v dd = v dd min. v oh output high voltage v dd -0.2 v i oh = -100 a, v dd = v dd min. v h supervoltage for a 9 pin 11.4 12.6 v ce# = oe# =v il , we# = v ih i h supervoltage current 200 a ce# = oe# = v il , we# = v ih , a 9 = v h max. for a 9 pin 396 pgm t9.1 t able 11: r eliability c haracteristics symbol parameter minimum specification units test method n end (1) endurance 10,000 cycles jedec standard a117 t dr (1) data retention 100 years jedec standard a103 v zap_hbm (1) esd susceptibility 2000 volts jedec standard a114 human body model v zap_mm (1) esd susceptibility 200 volts jedec standard a115 machine model i lth (1) latch up 100 + i dd ma jedec standard 78 note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this par ameter. 396 pgm t12.0
10 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 t able 13: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph (1) we# pulse width high 30 ns t cph (1) ce# pulse width high 30 ns t ds data setup time 30 ns t dh (1) data hold time 0 ns t ida (1) software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this pa rameter. 396 pgm t14.0 ac characteristics t able 12: r ead c ycle t iming p arameters v dd = 3.0-3.6v for sst39lf080/016 and 2.7-3.6v for sst39vf080/016 symbol parameter min max min max min max units t rc read cycle time 55 70 90 ns t ce chip enable access time 55 70 90 ns t aa address access time 55 70 90 ns t oe output enable access time 30 35 45 ns t clz (1) ce# low to active output 0 0 0 ns t olz (1) oe# low to active output 0 0 0 ns t chz (1) ce# high to high-z output 15 20 30 ns t ohz (1) oe# high to high-z output 15 20 30 ns t oh (1) output hold from address 0 0 0 ns change 396 pgm t13.2 sst39vf080/016-70 sst39lf080/016-55 sst39vf080/016-90
11 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 3: r ead c ycle t iming d iagram f igure 4: we# c ontrolled p rogram c ycle t iming d iagram 396 ill f02.1 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 396 ill f03.1 note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp
12 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 5: ce# c ontrolled p rogram c ycle t iming d iagram f igure 6: d ata # p olling t iming d iagram 396 ill f04.1 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 396 ill f05.1 note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. address a ms-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes
13 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 7: t oggle b it t iming d iagram f igure 8: we# c ontrolled c hip -e rase t iming d iagram 396 ill f06.1 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. 396 ill f08.1 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip-erase note: the device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 13) a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. t sce t wp
14 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 10: we# c ontrolled s ector -e rase t iming d iagram f igure 9: we# c ontrolled b lock -e rase t iming d iagram 396 ill f09.1 note: the device also supports ce# controlled block-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 13) a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa ba x oe# ce# six-byte code for block-erase t be t wp 396 ill f10.1 address a ms-0 note: the device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 13) a ms = most significant address a ms = a 19 for sst39lf/vf080 and a 20 for sst39lf/vf016. dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# six-byte code for sector-erase t se t wp
15 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 11: s oftware id e ntry and r ead f igure 12: cfi q uery e ntry and r ead 396 ill f12.0 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa 55 aa 98 396 ill f11.3 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90 note: device id = d9h for sst39lf/vf016 d8h for sst39lf/vf080
16 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 13: s oftware id e xit /cfi e xit 396 ill f13.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
17 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 14: ac i nput /o utput r eference w aveforms f igure 15: a t est l oad e xample ac test inputs are driven at v iht (0.9 v dd ) for a logic ? 1 ? and v ilt (0.1 v dd ) for a logic ? 0 ? . measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). inputs rise and fall times (10% ? 90%) are <5 ns. note: v it ? v input test v ot ? v output test v iht ? v input high test v ilt ? v input low test 396 ill f14.1 reference points output input v it v iht v ilt v ot 396 ill f15.1 to tester to dut c l
18 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 16: b yte -p rogram a lgorithm 396 ill f16.1 start load data: aah address: 5555h load data: 55h address: 2aaah load data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
19 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 17: w ait o ptions 396 ill f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
20 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 f igure 18: s oftware p roduct id/cfi c ommand f lowcharts 396 ill f18.1 load data: aah address: 5555h software product id entry command sequence load data: 55h address: 2aaah load data: 90h address: 5555h wait t ida read software id load data: aah address: 5555h cfi query entry command sequence load data: 55h address: 2aaah load data: 98h address: 5555h wait t ida read cfi data load data: aah address: 5555h software id exit/cfi exit command sequence load data: 55h address: 2aaah load data: f0h address: 5555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
21 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 f igure 19: e rase c ommand s equence 396 ill f19.1 load data: aah address: 5555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 10h address: 5555h load data: aah address: 5555h wait t sce chip erased to ffh load data: aah address: 5555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 5555h wait t se sector erased to ffh load data: aah address: 5555h block-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 50h address: ba x load data: aah address: 5555h wait t be block erased to ffh
22 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 device speed suffix1 suffix2 sst39xfxxx - xxx - xx - xx package modifier i = 40 pins k = 48 pins numeric = die modifier package type e = tsop (10mm x 20mm) b2 = tfbga (6mm x 8mm) temperature range c = commercial = 0 c to +70 c i = industrial = -40 c to +85 c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns 70 = 70 ns 90 = 90 ns device density 080 = 8 megabit 016 = 16 megabit voltage l = 3.0-3.6v v = 2.7-3.6v sst39lf080 valid combinations sst39lf080-55-4c-ei sst39lf080-55-4c-b2k sst39vf080 valid combinations sst39vf080-70-4c-ei sst39vf080-70-4c-b2k sst39vf080-90-4c-ei sst39vf080-90-4c-b2k sst39vf080-90-4i-ei sst39vf080-90-4i-b2k sst39lf016 valid combinations sst39vf016-55-4c-ei sst39vf016-55-4c-b2k sst39vf016 valid combinations sst39vf016-70-4c-ei SST39VF016-70-4C-B2K sst39vf016-90-4c-ei sst39vf016-90-4c-b2k sst39vf016-90-4i-ei sst39vf016-90-4i-b2k example: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
23 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 s71146 396-2 11/00 packaging diagrams 40-p in t hin s mall o utline p ackage (tsop) 10 mm x 20 mm sst p ackage c ode : ei 40.tsop-ei-ill.3 note: 1. complies with jedec publication 95 mo-142 cd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 10.10 9.90 .270 .170 1.05 0.95 .50 bsc 0.15 0.05 18.50 18.30 20.20 19.80 0.70 0.50 pin # 1 identifier
24 ? 2000 silicon storage technology, inc. 8 mbit / 16 mbit multi-purpose flash sst39lf080 / sst39lf016 / sst39vf080 / sst39vf016 data sheet s71146 396-2 11/00 silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com literature faxback 888-221-1178, international 732-544-2873 a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.23 0.04 1.10 0.10 0.15 6.00 0.20 0.335 0.035 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48ba tfbga.b2k.6x8-ill.1 note: 1. complies with the general requirements of jedec publication 95 mo-210, although some dimensions may be more stringent. (this specific outline variant has not yet been registered) 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 48-b all t hin p rofile f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b2k

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